| Ian Wilson 2004-05-14, 12:49 pm |
| I'm just getting to grips with Makefiles and have a question about how
best to reduce redundancy in the dependancy lines.
I've read my O'Reilly book (a bit dated), skimmed the man pages and
Googled a little without much success.
The software is compiled and then the object files are linked. This is a
4GL so the implicit .c .o etc stuff make knows about is not applicable.
I have something like ...
--------------------------------------------------------------------
%.obj : %.src
compile $<
fooprog_objs = foo_main.obj foo_mangle.obj foo_other.obj funky_lib.obj
barprog.objs = bar_part1.obj bar_part2.obj funky_lib.obj wow_lib.obj
bazprog.objs = bazmain.obj bazio.obj
quxprog.objs = qux.obj morequx.obj wow_lib.obj
# I also wish I knew a way to avoid so much ".obj" clutter above
fooprog.prg : ${fooprog.objs}
link -o $@ ${fooprog.objs}
barprog.prg : ${barprog.objs}
link -o $@ ${barprog.objs}
bazprog.prg : ${bazprog.objs}
link -o $@ ${bazprog.objs}
quxprog.prg : ${quxprog.objs}
link -o $@ ${quxprog.objs}
--------------------------------------------------------------------
Lets say the above works.
Is there any way of merging the dependancy & command lines into some
meta dependancy expression?
<anything>.prg : ${${<anything>}.objs}
link -o $@ ${${<anything>}.objs}
Thanks for any clues.
|