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Home > Archive > Unix Programming > November 2005 > Automatic variable $^ in makefile
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Automatic variable $^ in makefile
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| Alex Vinokur 2005-11-21, 2:49 am |
| Here is quote from
http://www.gnu.org/software/make/ma...ake.html#IDX586
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$^
The names of all the prerequisites, with spaces between them. For
prerequisites which are archive members, only the member named is used
(see section 11. Using make to Update Archive Files). A target has only
one prerequisite on each other file it depends on, no matter how many
times each file is listed as a prerequisite. So if you list a
prerequisite more than once for a target, the value of $^ contains just
one copy of the name.
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Any sample of using og $^ ?
Thanks.
Alex Vinokur
email: alex DOT vinokur AT gmail DOT com
http://mathforum.org/library/view/10978.html
http://sourceforge.net/users/alexvn
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| Paul Pluzhnikov 2005-11-21, 2:49 am |
| "Alex Vinokur" <alexvn@users.sourceforge.net> writes:
> Any sample of using og $^ ?
----------------------------------------
OBJS1 = main.o foo.o bar.o
OBJS2 = main.o foo.o baz.o
all: t1 t2
t1: $(OBJS1)
$(CC) -o $@ $^
t2: $(OBJS2) libZZZ.a
$(CXX) -o $@ $^
----------------------------------------
Cheers,
--
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