| Author |
how to generate dependent file in Makefile automatically?
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| DaVinci 2006-09-09, 1:21 pm |
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like this :
a.o:a.c a.h x.h y.h z.h
it is so easy to make a mistake .
so I want to know
how to generate the dependent relations in Makfile automatically?
I had tried in my ways ,but it isnot work.
a simple example given is hoped.
Thanks very much.
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| Pascal Bourguignon 2006-09-09, 1:21 pm |
| "DaVinci" <apple.davinci@gmail.com> writes:
> like this :
> a.o:a.c a.h x.h y.h z.h
> it is so easy to make a mistake .
> so I want to know
>
> how to generate the dependent relations in Makfile automatically?
> I had tried in my ways ,but it isnot work.
>
> a simple example given is hoped.
Put this in your Makefile:
SOURCES = module-a.c module-b.c module-c.c
APPLY = apply
CC = /usr/bin/gcc
CCMAKEDEPENDS = $(CC) -M $(INCLUDES)
Makefile.depend: Makefile $(SOURCES)
@echo '# -*- mode: makefile -*-' > Makefile.depend
@$(APPLY) "$(CCMAKEDEPENDS) $(CFLAGS)" $(SOURCES) >> Makefile.depend
-include Makefile.depend
--
__Pascal Bourguignon__ http://www.informatimago.com/
Nobody can fix the economy. Nobody can be trusted with their finger
on the button. Nobody's perfect. VOTE FOR NOBODY.
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| DaVinci 2006-09-09, 1:21 pm |
|
Pascal Bourguignon wrote:
> "DaVinci" <apple.davinci@gmail.com> writes:
>
>
> Put this in your Makefile:
>
>
> SOURCES = module-a.c module-b.c module-c.c
>
> APPLY = apply
> CC = /usr/bin/gcc
> CCMAKEDEPENDS = $(CC) -M $(INCLUDES)
what is the vaule of variable $INCLUDE ?
>
> Makefile.depend: Makefile $(SOURCES)
> @echo '# -*- mode: makefile -*-' > Makefile.depend
> @$(APPLY) "$(CCMAKEDEPENDS) $(CFLAGS)" $(SOURCES) >> Makefile.depend
could you please explain the codes for me?
>
> -include Makefile.depend
>
>
>
> --
> __Pascal Bourguignon__ http://www.informatimago.com/
>
> Nobody can fix the economy. Nobody can be trusted with their finger
> on the button. Nobody's perfect. VOTE FOR NOBODY.
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| Pascal Bourguignon 2006-09-10, 1:26 am |
| "DaVinci" <apple.davinci@gmail.com> writes:
> Pascal Bourguignon wrote:
>
> what is the vaule of variable $INCLUDE ?
Whatever you want. Usually, you put there the include directives for
your project, something like:
INCLUDE= -I/usr/local/lib/somelibrary -I../someotherlib/
Similarly, you set CFLAGS to some flags needed to compile your C
sources, like for example:
CFLAGS=-Wall -g -O2
>
> could you please explain the codes for me?
You could try to read more documentation.
man make
info make
lynx http://www.google.com/search?q=gnu+make
man apply
man gcc
--
__Pascal Bourguignon__ http://www.informatimago.com/
Until real software engineering is developed, the next best practice
is to develop with a dynamic system that has extreme late binding in
all aspects. The first system to really do this in an important way
is Lisp. -- Alan Kay
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| reverse 2006-09-11, 1:32 am |
| On 2006-09-09, DaVinci <apple.davinci@gmail.com> wrote:
>
> like this :
> a.o:a.c a.h x.h y.h z.h
> it is so easy to make a mistake .
> so I want to know
>
> how to generate the dependent relations in Makfile automatically?
> I had tried in my ways ,but it isnot work.
>
> a simple example given is hoped.
> Thanks very much.
Hi, i wrote this:
wget http://akabzone.it/unix-in-shell/ba...ad/gamble.sh.gz
Put gamble.sh.gz in directory where they are all .c and .h file, then:
$ gamble -d
-d = default (executable in makefile run_dd_mm_yyyy)
And then run make; it's simple, but it works well for little
project.
Note: it's written in Italian, sorry.
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| Itamar 2006-09-16, 7:38 pm |
| On 2006-09-09 08:17:25 -0400, Pascal Bourguignon <pjb@informatimago.com> said:
> "DaVinci" <apple.davinci@gmail.com> writes:
>
>
> Put this in your Makefile:
>
>
> SOURCES = module-a.c module-b.c module-c.c
>
> APPLY = apply
> CC = /usr/bin/gcc
> CCMAKEDEPENDS = $(CC) -M $(INCLUDES)
>
> Makefile.depend: Makefile $(SOURCES)
> @echo '# -*- mode: makefile -*-' > Makefile.depend
> @$(APPLY) "$(CCMAKEDEPENDS) $(CFLAGS)" $(SOURCES) >> Makefile.depend
>
> -include Makefile.depend
e-l-e-g-a-n-t!
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