|
Home > Archive > Unix Shell > January 2006 > Makefiles involving files in different directories requiring different compilers
You are viewing an archived Text-only version of the thread.
To view this thread in it's original format and/or if you want to reply to
this thread please [click here]
| Author |
Makefiles involving files in different directories requiring different compilers
|
|
| hzmonte@hotmail.com 2006-01-09, 6:02 pm |
| Let's say I have a directory "work" and a subdirectory "tools" under
it. Both have their own Makefiles. tools are also used by files other
than those in work. I have in work's Makefile something like this:
OBJ = a.o b.o ../tools/c.o ../tools/d.o
myexec: $(OBJS)
g++ -c main.cc -o myexec
%.o: %.cc
g++ -c $< -o $@
And in tool's Makefile:
%.o: %.c
gcc -c $< -o $@
That is, the files in work are C++ programs whereas those in tools are
C programs; and myexec depends on files in tools.
The way work's Makefile is now written would compile c and d using g++,
if they are outdated, but not gcc. That causes a problem for me. What
is the best way to write the Makefiles so that c and d are always
compiled using gcc? Thx.
| |
| Stachu 'Dozzie' K. 2006-01-09, 6:02 pm |
| On 09.01.2006, hzmonte@hotmail.com <hzmonte@hotmail.com> wrote:
> Let's say I have a directory "work" and a subdirectory "tools" under
> it. Both have their own Makefiles. tools are also used by files other
> than those in work. I have in work's Makefile something like this:
> OBJ = a.o b.o ../tools/c.o ../tools/d.o
> myexec: $(OBJS)
> g++ -c main.cc -o myexec
> %.o: %.cc
> g++ -c $< -o $@
> And in tool's Makefile:
> %.o: %.c
> gcc -c $< -o $@
> That is, the files in work are C++ programs whereas those in tools are
> C programs; and myexec depends on files in tools.
> The way work's Makefile is now written would compile c and d using g++,
> if they are outdated, but not gcc. That causes a problem for me. What
> is the best way to write the Makefiles so that c and d are always
> compiled using gcc?
You mean "how to execute compilation of c.o and d.o in ../tools/
directory accordingly to ../tools/Makefile", don't you? You need to add
an additional target:
#v+
.../tools/%.o:
$(MAKE) -C $(dir $@) $(notdir $@)
# or
# cd $(dir $@); $(MAKE) $(notdir $@)
#v-
I tried to write this target as general as possible, but I don't know
any other make utility than GNU make so I probably used something
GNU make-specific. I hope you catch the idea.
--
Feel free to correct my English
Stanislaw Klekot
| |
| Chris F.A. Johnson 2006-01-09, 6:02 pm |
| On 2006-01-09, hzmonte@hotmail.com wrote:
> Let's say I have a directory "work" and a subdirectory "tools" under
> it. Both have their own Makefiles. tools are also used by files other
> than those in work. I have in work's Makefile something like this:
> OBJ = a.o b.o ../tools/c.o ../tools/d.o
> myexec: $(OBJS)
> g++ -c main.cc -o myexec
>%.o: %.cc
> g++ -c $< -o $@
> And in tool's Makefile:
>%.o: %.c
> gcc -c $< -o $@
> That is, the files in work are C++ programs whereas those in tools are
> C programs; and myexec depends on files in tools.
> The way work's Makefile is now written would compile c and d using g++,
> if they are outdated, but not gcc. That causes a problem for me. What
> is the best way to write the Makefiles so that c and d are always
> compiled using gcc? Thx.
A Makefile is not a shell script; you should ask in a group
dedicated to programming, or a GNU group such as gnu.gcc.help.
--
Chris F.A. Johnson, author | <http://cfaj.freeshell.org>
Shell Scripting Recipes: | My code in this post, if any,
A Problem-Solution Approach | is released under the
2005, Apress | GNU General Public Licence
|
|
|
|
|