| Author |
Why use $() for env vars?
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| I have an example make file which has the following lines:
CC = gcc
CFLAGS = -g -Wall
INSTALL_PROGRAM = install
$(MAKE) CC="$(CC)" CFLAGS="$(CFLAGS)"
Why do they use CC=$(CC) and not CC=$CC ?
Thanks.
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| Xicheng Jia 2006-09-19, 7:25 pm |
| yusuf wrote:
> I have an example make file which has the following lines:
>
> CC = gcc
> CFLAGS = -g -Wall
> INSTALL_PROGRAM = install
>
> $(MAKE) CC="$(CC)" CFLAGS="$(CFLAGS)"
>
> Why do they use CC=$(CC) and not CC=$CC ?
$(..) in Makefile is completely different from that in shell. check out
this page:
http://www.cis.ksu.edu/VirtualHelp/....Reference.html
Xicheng
--
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|
| x=abc
echo $x # $var_nm to retrieve value from a variable var_nm
x=$(ls) # execute ls and return with file listing
# this is the syntax to get return value of a command
you can also use
x=`ls`
to do the same as above
yusuf wrote:
> I have an example make file which has the following lines:
>
> CC = gcc
> CFLAGS = -g -Wall
> INSTALL_PROGRAM = install
>
> $(MAKE) CC="$(CC)" CFLAGS="$(CFLAGS)"
>
> Why do they use CC=$(CC) and not CC=$CC ?
>
> Thanks.
| |
| Bruce Barnett 2006-09-20, 1:32 am |
| "yusuf" <yusufm@gmail.com> writes:
> I have an example make file which has the following lines:
>
> CC = gcc
> CFLAGS = -g -Wall
> INSTALL_PROGRAM = install
>
> $(MAKE) CC="$(CC)" CFLAGS="$(CFLAGS)"
>
> Why do they use CC=$(CC) and not CC=$CC ?
That's what "make" does.
I'm not sure of this, but "make" may be older than the Bourne shell.
Make was created because the guys at Bell realized that software development
was composed of 4 steps:
1) Think
2) Edit
3) Make the program
4) Run the program
so they decided to create a program that handled all of the steps
needed to "make" a new version.
This was quite a novel idea. Normally we has to recompile everything.
I was also amazed that compiling was so
fast in the Unix environment - compared to other OSes I was using at
the time.
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| William 2006-09-20, 1:29 pm |
| "yusuf" <yusufm@gmail.com> wrote in message
news:1158697923.574185.213630@e3g2000cwe.googlegroups.com...
> I have an example make file which has the following lines:
>
> CC = gcc
> CFLAGS = -g -Wall
> INSTALL_PROGRAM = install
>
> $(MAKE) CC="$(CC)" CFLAGS="$(CFLAGS)"
>
> Why do they use CC=$(CC) and not CC=$CC ?
Because in make CC=$CC would set CC to the value "gccC".
Without the parentheses, make treats only the first character
after the $ as a variable name. (So CC=$C is the same as
CC=$(C), but CC=$CC is not the same as CC=$(CC).)
-Wm
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