I have this command line that is used several hundred times throught
the Makefile.  More very similar exist, commands slightly different.  I
would like to reduce it to a $(call ...  or some other format.  I think
I know how to do it by usng severy define statements, but It would be
nice to have other options.
The following is built by a PERL script. There are several hundred
identical with the exception of _<proj>_<bb>_<topic> in the target.
These 3 items change at every rule. That is why I do it with a perl
script.  I use the "; \" to reduce the sheer # of processes teh
Makefile must spawn.  Estimate 200k+.  Effort to reduce system load for
max parallel processing.
##
## build_<proj>_<bb>_<topic>
##
# project : lde , building block : ld_exp , topic : reg
build_lde_ld_exp_reg :
@${EXEC_LOG} ${MKDIR} ${SRC_TREE}/lde/ld_exp/reg/inc -proj ld
e
-bb ld_exp -topic reg; \
${EXEC_LOG}   ${MKDIR} ${SRC_TREE}/lde/ld_exp/reg/src -proj l
de
-bb ld_exp -topic reg; \
${EXEC_LOG}   ${MKDIR} ${SRC_TREE}/lde/ld_exp/shr -proj lde -
bb
ld_exp; \
${EXEC_LOG}   ${MKDIR} ${SRC_TREE}/lde/ld_exp/pub -proj lde -
bb
ld_exp; \
${EXEC_LOG}   ${MKDIR} ${PRD_TREE}/lde/bin -proj lde; \
${EXEC_LOG}   ${MKDIR} ${PRD_TREE}/lde/lib -proj lde; \
${EXEC_LOG}   ${MKDIR} ${PRD_TREE}/lde/ld_exp -proj lde -bb
ld_exp ; \
${EXEC_LOG}   $(CP) files_d_make/make.include.lde
${SRC_TREE}/lde/make.include -proj lde ; \
${EXEC_LOG}   $(CP) files_d_make/make.include.lde.ld_exp \
${SRC_TREE}/lde/ld_exp/make.include -proj
lde -bb ld_exp ;\
${EXEC_LOG}   $(CP) files_d_make/make.include.lde.ld_exp.reg \
${SRC_TREE}/lde/ld_exp/reg/make.include
-proj lde -bb ld_exp -topic reg ;\

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Be aware that you're talking exclusively about GNU make here.  None of
this will be portable to other versions of make.  If that's what you
want you might consider asking these questions in a forum dedicated to
GNU make in particular, rather than UNIX programming in general.


%% "billy" <bp1497@att.com> writes:

b> The following is built by a PERL script. There are several hundred
b> identical with the exception of _<proj>_<bb>_<topic> in the target.
b> These 3 items change at every rule.

But is that the ONLY thing that changes with every rule?  Do none of the
contents of the rule change?  If so then it's pretty simple to use a
variable to contain this script.

b> That is why I do it with a PERL script.  I use the "; \" to reduce
b> the sheer # of processes teh Makefile must spawn.  Estimate 200k+.
b> Effort to reduce system load for max parallel processing.

First, you should be separating the different commands with "&&" instead
of ";".  If you use ";" then if one command in the middle fails the rest
will continue processing; the only way make will see any failure is if
the LAST one fails.

If you use "&&" instead then as soon as one fails, the rest will not
continue and make will get an error code.


Second, GNU make does have a "fast path" capability: if it determines
that the command to be invoked is "simple enough", which means it
doesn't make use of any shell facilities like shell variables,
pipelining, ";", "&&", "||", etc., then GNU make will fork/exec the
command directly and not spawn a shell at all.

So, IF all your commands are that simple then you will save yourself one
shell invocation per target by using one line per command rather than
putting them all in the same line.

However, if you're not sure you should continue to use the method you're
using (but with "&&" as above), since one extra shell per target is
better than one extra shell per line.

--
----------------------------------------------------------------------------
---
Paul D. Smith <psmith@gnu.org>          Find some GNU make tips at:
http://www.gnu.org                      http://make.paulandlesley.org
"Please remain calm...I may be mad, but I am a professional." --Mad Scientis
t

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