Hi,

I'm having a makefile problem when multiple files appear as
dependencies and targets in rules.

For example, let's say that only the file d intially exists and
"myprog d" generates b and c.

If I have the following in my makefile:

a: b c
otherprog
b c: d
myprog d

Running "make -n", will show the following:
myprog d
myprog d
otherprog

as "make" traverses the dependency tree from left to right depth first
it seems.

Is there any way to make "make" run "myprog d" a single time instead
of twice (and at the same time not call "myprog d" unnecessarily if b
and c already exist and haven't bee modified)?

The following hack isn't suitable:
a: b
b: c
otherprog
c: d
myprog d

This is because myprog will always at least "touch" b and c, and thus
"myprog d" will always execute, even if b and c hadn't be modified.

Thanks for any help.

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On Nov 17, 5:00 pm, Morfys <morfyss...@gmail.com> wrote:
> Hi,
>
> I'm having a makefile problem when multiple files appear as
> dependencies and targets in rules.
>
> For example, let's say that only the file d intially exists and
> "myprog d" generates b and c.
>
> If I have the following in my makefile:
>
> a: b c
>     otherprog
> b c: d
>     myprog d
>
> Running "make -n", will show the following:
> myprog d
> myprog d
> otherprog

It looks like make is smart enough to re-check the existence of both
targets anyway - this seems to work correctly for me:

$ make clean
rm -f b c

$ make -n
cp d b; cp d c
cp d b; cp d c
ls -l b c

$ make
cp d b; cp d c
ls -l b c
-rw-r--r--   1 toby  toby  0 Nov 17 19:56 b
-rw-r--r--   1 toby  toby  0 Nov 17 19:56 c

$ cat Makefile
myprog=cp d b; cp d c
a: b c
ls -l b c
b c: d
$(myprog)
clean : ; rm -f b c


>
> as "make" traverses the dependency tree from left to right depth first
> it seems.
>
> Is there any way to make "make" run "myprog d" a single time instead
> of twice (and at the same time not call "myprog d" unnecessarily if b
> and c already exist and haven't bee modified)?
>
> The following hack isn't suitable:
> a: b
> b: c
>     otherprog
> c: d
>     myprog d
>
> This is because myprog will always at least "touch" b and c, and thus
> "myprog d" will always execute, even if b and c hadn't be modified.
>
> Thanks for any help.

[ Post a follow-up to this message ]

thank you very much.  I was fooled by the output of "make -n".

In your example,
make -n

shows:

cp d b; cp d c
cp d b; cp d c
ls -l b c

where as, in reality running:
make

causes only the following to execute:
cp d b; cp d c
ls -l b c

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