Hello,
I have a master make file that I am porting from Windows to linux, it
is working reasonably well (I am still getting kinks out though).
The problem I am seeing is that, everytime it calls $(MAKE) for target
library to be made, the recursive make spits out to stdout the entire
directory listing of the current directory.  Then it outputs:
gmake[1]: Entering directory `/home/sourceDirectory'
The make succeeds, then it shows:
gmake[1]: Leaving directory `/home/sourceDirectory'

Same exact result if I use make instead of gmake.

Any idea why the directory listing occurs?  I plan to have unattended
makes pipe output to a file so I can check for build problems later,
and I don't want to see an entire large directory listing included for
each of approx 20 sub makefiles.
Thanks in advance,
david.kaatz  AT intermec DOT com

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"kaatzd@hotmail.com" <kaatzd@hotmail.com> writes:

> I have a master make file that I am porting from Windows to linux, it
> is working reasonably well (I am still getting kinks out though).
> The problem I am seeing is that, everytime it calls $(MAKE) for target
> library to be made, the recursive make spits out to stdout the entire
> directory listing of the current directory.  Then it outputs:
> gmake[1]: Entering directory `/home/sourceDirectory'
> The make succeeds, then it shows:
> gmake[1]: Leaving directory `/home/sourceDirectory'
>
> Same exact result if I use make instead of gmake.

On linux, make and gmake are the same thing.

> Any idea why the directory listing occurs?  I plan to have
> unattended makes pipe output to a file so I can check for build
> problems later, and I don't want to see an entire large directory
> listing included for each of approx 20 sub makefiles.  Thanks in
> advance,

It shouldn't be doing that. What's the exact command you're using, and
how do you invoke make from the command line?

http://www.fsf.org/software/make/ma...make.html#SEC59

Joe
--
If you don't think too good, don't think too much
- Ted Williams

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Exact command:
@$(MAKE) -f $*$(PLATFORM_CODE).mak platform=$(platform) LIBTYPE=dll all

>From command line:
make -f masterLX.mak platform=linux component=shmem all
Thanks in advance,
Dave

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"kaatzd@hotmail.com" <kaatzd@hotmail.com> writes:

> Exact command:
> @$(MAKE) -f $*$(PLATFORM_CODE).mak platform=$(platform) LIBTYPE=dll all

What's the $* doing there? What does $(PLATFORM_CODE) expand to? Try
printing out what it means at that point and see if there's a '*' that
the shell is expanding.

Also, can you post the actual output of the command? This doesn't
produce a directory listing on my linux box.
 
> make -f masterLX.mak platform=linux component=shmem all

Joe
--
If you don't think too good, don't think too much
- Ted Williams

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%% "kaatzd@hotmail.com" <kaatzd@hotmail.com> writes:

kc> Exact command:
kc> @$(MAKE) -f $*$(PLATFORM_CODE).mak platform=$(platform) LIBTYPE=dll all

The very first thing to do when trying to figure out why a command
script is not behaving as you'd expect is to remove all line suppression
characters ("@") and see exactly how your command line is being
expanded.

Also you can use "make -n" which will print the commands normally hidden
by "@".

--
----------------------------------------------------------------------------
---
Paul D. Smith <psmith@gnu.org>          Find some GNU make tips at:
http://www.gnu.org                      http://make.paulandlesley.org
"Please remain calm...I may be mad, but I am a professional." --Mad Scientis
t

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Sorry Joe,

Problem solved.  See below.

I should have given you more.
Here is the inference rule being invoked:
.mak.dll:
@$(ECHO)  ****************************************
******
@$(ECHO)  ****************************************
******
@$(ECHO)  ****************************************
******
@$(ECHO) Building $* .mak files
@$(COPY) BBVersionInfo.h productverinfo.h
@$(MAKE) -f $*$(PLATFORM_CODE).mak platform=$(platform) LIBTYPE=dll
all

So $* expands to the name of the target component, and $(PLATFORM_CODE)
is defined (based on command line platform=xxx portion) to be LX, so
that I can differentiate makefiles and targets for different platforms.

I thought I previously tried commenting out the ECHO lines and the COPY
line with no change in behavior.

I just tried that again, and the problem went away.  Apparently the
echo lines (ECHO=echo) with * in them screw it up, somehow being
interpreted as wildcards??

Thanks for your willingness to help, I'm sure I'll have more questions
along the way.

Dave

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%% "kaatzd@hotmail.com" <kaatzd@hotmail.com> writes:

kc> @$(ECHO)  ****************************************
******

kc> I just tried that again, and the problem went away.  Apparently the
kc> echo lines (ECHO=echo) with * in them screw it up, somehow being
kc> interpreted as wildcards??

Certainly.

If you run "echo *********" on the command line what will it do?  The
same thing happens when make invokes a shell to run it.

If you don't want globbing characters like *, [], and ? interpreted by
the shell be sure to enclose them in quotes:

@$(ECHO) " ****************************************
******"

--
----------------------------------------------------------------------------
---
Paul D. Smith <psmith@gnu.org>          Find some GNU make tips at:
http://www.gnu.org                      http://make.paulandlesley.org
"Please remain calm...I may be mad, but I am a professional." --Mad Scientis
t

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"kaatzd@hotmail.com" <kaatzd@hotmail.com> writes:

> Sorry Joe,
>
> Problem solved.  See below.

[...]

> Thanks for your willingness to help, I'm sure I'll have more
> questions along the way.

Well, I'm willing to try, but since Paul's watching the thread, I'll
leave it to him. He knows more about make than I ever will.

Joe
--
If you don't think too good, don't think too much
- Ted Williams

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