After takin a swig o' Arrakan spice grog, "Ranando King" <rk@magictouchcorp.com> belched out
:
> The main reason I didn't touch the IHT performance issues is because
> I'm making what might be a terrible assumption: that the Niagara
> chip will be using cores with truely "parallel thread"
> processing. IHT isn't quite that, which is the reason it suffers
> such performance hits for software not specifically designed to
> handle it. Also, the fact that you can enable HT on SMP makes it
> somewhat ok to ignore those issues for this lopsided
> comparison. Now... if we ignore the IHT features altogether as well
> as Niagara's parallel threads, we basically end up comparing a
> single processor to an 8 processor SMP system without the SMP
> bottlenecks. Under such conditions, the statements I made still
> hold. There isn't that much work to be done to support such a
> system. Current day applications will still benefit greatly from the
> decreased process/cpu core ratio.

This points to another issue, namely that of the scalability of memory
bandwidth.

Intel's implementation of HyperThreading only appears to lead to
around 20% increases in CPU throughput, and that being the best case
scenario.

If your bottleneck is memory access, then you won't get as much as a
20% improvement from hyperthreading, and might even watch performance
get WORSE, not better.

A situation where there are 16 CPU cores on one chip is entirely
likely to exacerbate the situation; if they are all fighting for
access to a single memory bus, that means memory bandwidth will be the
entirety of the system bottleneck.  I'd be really surprised if 16 CPUs
could get materially more work done than 8 if they are sharing one
memory bus.

NUMA is, of course, a good answer to that, but adds considerable
hardware complications.  Each CPU has to have its own memory bus,
which means an impressively increased pinout requirement for the CPU
chip...
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