If you read the article, the Niagara system will be using more than 1 memory
controller. The memory bandwidth bottleneck will not be much of an issue...
if any at all. The article also mentioned a second version of the chip that
will use what I guess is some kind of paging method to decrease the # of
pins required at the cost of additional latency on memory fetches. But the
design of the chip should hide some if not most of the latency.

All-in-all, this Niagara setup looks like it's approaching the idea of a
system design I imagined building for myself about 4 years ago.

"Christopher Browne" <cbbrowne@acm.org> wrote in message
news:2vv1plF2pcosbU3@uni-berlin.de...
> This points to another issue, namely that of the scalability of memory
> bandwidth.
>
> Intel's implementation of HyperThreading only appears to lead to
> around 20% increases in CPU throughput, and that being the best case
> scenario.
>
> If your bottleneck is memory access, then you won't get as much as a
> 20% improvement from hyperthreading, and might even watch performance
> get WORSE, not better.
>
> A situation where there are 16 CPU cores on one chip is entirely
> likely to exacerbate the situation; if they are all fighting for
> access to a single memory bus, that means memory bandwidth will be the
> entirety of the system bottleneck.  I'd be really surprised if 16 CPUs
> could get materially more work done than 8 if they are sharing one
> memory bus.
>
> NUMA is, of course, a good answer to that, but adds considerable
> hardware complications.  Each CPU has to have its own memory bus,
> which means an impressively increased pinout requirement for the CPU
> chip...
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