Below is my makefile, and list of files:

<files>
Obj1.cc
Obj1.h
Obj2.cc
Obj2.h
Obj3.cc
Obj3.h
demo1.cc
demo2.cc
</files>

<makefile>
OBJECTS = Obj1.o Obj2.o Obj3.o

.cc.o:
$(CC) -c $(DEFINES) $(CCFLAGS) $< $(LIBS)

.cc.exe: libMyLib.a
$(CC) -o $@ $(DEFINES) $(CCFLAGS) $(INCS) $< libMyLib.a $(LIBS)

demos: demo1.exe demo2.exe

libMyLib.a:$(OBJECTS)
$(AR) cvr $@ $(OBJECTS)

clean:
\rm *.o *.a *.exe
</makefile>

Problem 1:
When I do a make, libMyLib.a is created, great!  But demo1.exe and
demo2.exe are not created.  The error message is don't know how to make
target 'demo1.exe'.
Does anyone know what none of the demo*.exe's will build?


Problem2:
when I alter a *.h file, the Object does not get recompiled.
How can I build this into my .cc.o and .cc.exe rules?

Thanks,

~S

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Shea Martin wrote:
<snip>
quote:

> Obj3.cc
> Obj3.h
> demo1.cc

<snip>
quote:

> .cc.o:

<snip>
quote:

> .cc.exe: libMyLib.a

<snip>
quote:

> When I do a make, libMyLib.a is created, great!  But demo1.exe and
> demo2.exe are not created.  The error message is don't know how to make
> target 'demo1.exe'.
> Does anyone know what none of the demo*.exe's will build?


Your rules generate *.cc.exe from *.cc, so demo1.cc will generate
demo1.cc.exe, not demo1.exe. You also don't list your "demos" target as
ad ependency on any of the other targets.
quote:

>
> Problem2:
> when I alter a *.h file, the Object does not get recompiled.
> How can I build this into my .cc.o and .cc.exe rules?


Just list them on the dependencies line for the appropriate target(s).

Ed.

[ Post a follow-up to this message ]

Shea Martin wrote:
quote:

> Below is my makefile, and list of files:
>
> <files>
> Obj1.cc
> Obj1.h
> Obj2.cc
> Obj2.h
> Obj3.cc
> Obj3.h
> demo1.cc
> demo2.cc
> </files>
>
> <makefile>
> OBJECTS = Obj1.o Obj2.o Obj3.o
>
> .cc.o:
>     $(CC) -c $(DEFINES) $(CCFLAGS) $< $(LIBS)
>
> .cc.exe: libMyLib.a
>     $(CC) -o $@ $(DEFINES) $(CCFLAGS) $(INCS) $< libMyLib.a $(LIBS)
>
> demos: demo1.exe demo2.exe
>
> libMyLib.a:$(OBJECTS)
>     $(AR) cvr $@ $(OBJECTS)
>
> clean:
>     \rm *.o *.a *.exe
> </makefile>
>
> Problem 1:
> When I do a make, libMyLib.a is created, great!  But demo1.exe and
> demo2.exe are not created.  The error message is don't know how to make
> target 'demo1.exe'.
> Does anyone know what none of the demo*.exe's will build?
>
>
> Problem2:
> when I alter a *.h file, the Object does not get recompiled.
> How can I build this into my .cc.o and .cc.exe rules?
>
> Thanks,
>
> ~S
>

Solved:
needed to add this line to make file:

SUFFIXES = .o .cc .exe
.SUFFIXES : $(SUFFIXES)

I am not really sure why I need the second line, but anyway, it works.

~S

[ Post a follow-up to this message ]

Shea Martin wrote:
quote:

> Shea Martin wrote:
> 
> Solved:
> needed to add this line to make file:
>
> SUFFIXES = .o .cc .exe
> .SUFFIXES : $(SUFFIXES)
>
> I am not really sure why I need the second line, but anyway, it works.
>
> ~S
>

BTW, still need ans. to Problem 2:

TIA,
~S

[ Post a follow-up to this message ]

Shea Martin wrote:
[...]
quote:

> Solved:
> needed to add this line to make file:
>
> SUFFIXES = .o .cc .exe
> .SUFFIXES : $(SUFFIXES)
>
> I am not really sure why I need the second line, but anyway, it works.
>


Hi.
Actually the 2nd line is the only one you need:
.SUFFIXES: .exe
(.cc and .o are not needed, but they don't hurt either)

You are telling make that .exe is a know (to make) extension.
That way files ending in .exe will be handled by the .cc.exe
stuff.

As for your 2nd question, I'm afraid you must list all dependencies
explicitly. For example, at the end of the makefile you can *add* the
following:

Obj1.o: Obj1.cc Obj1.h
[etc]

--
carlos

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Carlos J. G. Duarte wrote:
quote:

> Shea Martin wrote:
> [...]
> 
>
> Hi.
> Actually the 2nd line is the only one you need:
> .SUFFIXES: .exe
> (.cc and .o are not needed, but they don't hurt either)


Thanks.
quote:

> As for your 2nd question, I'm afraid you must list all dependencies
> explicitly. For example, at the end of the makefile you can *add* the
> following:
>
> Obj1.o: Obj1.cc Obj1.h
> [etc]
>


I was afraid of that.  I wrote a small shell script with parses
genereates a makefile for me, with proper dependancies.  Not as elegant
as I would like, but still a time saver.

Thanks,

~S

[ Post a follow-up to this message ]

Carlos J. G. Duarte wrote:
<snip>
quote:

> As for your 2nd question, I'm afraid you must list all dependencies
> explicitly. For example, at the end of the makefile you can *add* the
> following:
>
> Obj1.o: Obj1.cc Obj1.h
> [etc]
>


Not necessarily. For example, with GNU make this rule:

%: %.c %.h
gcc -o $@ $<

uses the "%" operator to indicate the target name in the prerequisite
list, so if you say "make x", then the above rule is equivalent to:

x: x.c x.h
gcc -o x x.c

So, you should be able to say something like:

%.cc.o: %.cc %.h
$(CC) -c $(DEFINES) $(CCFLAGS) $< $(LIBS)

Take a look at the GNU make info page to work out the details if that
doesn't work as-is.

Ed.

[ Post a follow-up to this message ]

Ed Morton wrote:
quote:

>
>
> Carlos J. G. Duarte wrote:
> <snip>
> 
>
> Not necessarily. For example, with GNU make this rule:
>
> %: %.c %.h
>         gcc -o $@ $<
>
> uses the "%" operator to indicate the target name in the prerequisite
> list, so if you say "make x", then the above rule is equivalent to:
>
> x: x.c x.h
>     gcc -o x x.c
>
> So, you should be able to say something like:
>
> %.cc.o: %.cc %.h
>     $(CC) -c $(DEFINES) $(CCFLAGS) $< $(LIBS)
>
> Take a look at the GNU make info page to work out the details if that
> doesn't work as-is.
>
>     Ed.
>
>

Sweet.  "%.cc.o: %.cc %.h" did not work for me, but "%.o: %.cc %.h" did!
It is not quite as complete as my script (below), but it is much more
simple.  I think my script will get tossed.  Thanks.

<script>
#!/bin/bash

SUFFIX="*.cc *.cpp"

echo ""
echo "# DEPS generated by $0:"

for FILE in $SUFFIX; do

if ! [ -f "$FILE" ]; then
continue
fi

PFX=${FILE%.*}
DEPS=$FILE

if [ -f "$.h" ]; then
DEPS="$DEPS $PFX.h"
fi

for INC in $(grep '#include \"' $FILE | cut -f2 -d\"); do
DEPS="$DEPS $INC"
done

echo "$PFX.o: $DEPS"

done
</script>

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