Hi,

I am unsure if this is the correct newsgroup, so please direct me to the
proper one if my question is answered elsewhere.

I would like to write a general rule in a Makefile for a VHDL compiler. The
input file is source.vhd and the output file is SOURCE.syn. Is there a
succinct way of expressing this as a rule (there are several files I want to
compile and I would rather not have to write separate rules for each case)?

If I write it so:

%.syn : %.vhd
$(VHDLCOMP) $(VFLAGS) $<

then make will not get the dependency information correctly: it will check t
o
see if 'SOURCE.vhd' is newer than the target (but I want 'source.vhd' to be
checked). The name of the file produced cannot be specified as far as I can
tell, so I cannot just tell the compiler to output 'source.syn'.

I tried the following:

LOWERCASE=echo $* | tr '[:upper:]' '[:lower:]'

%.syn : $(LOWERCASE:sh).vhd
${VHDLCOMP} ${VFLAGS} $<

But make doesn't know how to make SOURCE.syn. I am trying this on Solaris
(SunOS call 5.8 Generic_108528-14 sun4u sparc SUNW,Ultra-5_10) with
'/usr/ccs/bin/make'.

When I test out $(LOWERCASE:sh) it works as expected when executed as a comm
and
but it does not work when it is used as a rule. Can macros be used in rules
this way? Any suggestions?

[ Post a follow-up to this message ]

gthor.edit.pe@ee.ryerson.ca wrote:
> I am unsure if this is the correct newsgroup, so please direct me to the
> proper one if my question is answered elsewhere.

> I would like to write a general rule in a Makefile for a VHDL compiler. Th
e
> input file is source.vhd and the output file is SOURCE.syn. Is there a
> succinct way of expressing this as a rule (there are several files I want 
to
> compile and I would rather not have to write separate rules for each case)?[/vbcol
]
[vbcol=seagreen]
> If I write it so:

> %.syn : %.vhd
> 	$(VHDLCOMP) $(VFLAGS) $<

> then make will not get the dependency information correctly: it will check
 to
> see if 'SOURCE.vhd' is newer than the target (but I want 'source.vhd' to b
e
> checked). The name of the file produced cannot be specified as far as I ca
n
> tell, so I cannot just tell the compiler to output 'source.syn'.

> I tried the following:

> LOWERCASE=echo $* | tr '[:upper:]' '[:lower:]'

> %.syn : $(LOWERCASE:sh).vhd
> 	${VHDLCOMP} ${VFLAGS} $<

> But make doesn't know how to make SOURCE.syn. I am trying this on Solaris
> (SunOS call 5.8 Generic_108528-14 sun4u sparc SUNW,Ultra-5_10) with
> '/usr/ccs/bin/make'.

> When I test out $(LOWERCASE:sh) it works as expected when executed as a co
mmand
> but it does not work when it is used as a rule. Can macros be used in rule
s
> this way? Any suggestions?

I can't say about your version of make but with GNU make you can do
it like this:

%.syn: $($(shell echo % | tr "A-Z" "a-z"):=.vhd)

Perhaps your version allows something similar....

Regards, Jens
--
\   Jens Thoms Toerring  ___  Jens.Toerring@physik.fu-berlin.de
\__________________________  http://www.toerring.de

[ Post a follow-up to this message ]

Jens.Toerring@physik.fu-berlin.de wrote: 
[vbcol=seagreen] 
[vbcol=seagreen] 
[vbcol=seagreen] 
[vbcol=seagreen] 
[vbcol=seagreen]
> I can't say about your version of make but with GNU make you can do
> it like this:

> %.syn: $($(shell echo % | tr "A-Z" "a-z"):=.vhd)

> Perhaps your version allows something similar....

The snippets I posted are supposed to achive the same thing by substituting
the results of the shell and it works in the Makefile, but not when it is in
the dependency part of the rule.

I am unsure of how to specify arbitrary rules (make seems to assume that the
target will have the same suffix as the dependency) in the case of implied
rules.

[ Post a follow-up to this message ]

gthorpe@ee.ryerson.ca wrote:
> Jens.Toerring@physik.fu-berlin.de wrote: 
[vbcol=seagreen] 
[vbcol=seagreen] 
[vbcol=seagreen] 
[vbcol=seagreen] 
[vbcol=seagreen] 
[vbcol=seagreen] 
[vbcol=seagreen] 
[vbcol=seagreen]
> The snippets I posted are supposed to achive the same thing by substitutin
g
> the results of the shell and it works in the Makefile, but not when it is 
in
> the dependency part of the rule.

> I am unsure of how to specify arbitrary rules (make seems to assume that t
he
> target will have the same suffix as the dependency) in the case of implied
> rules.

Sorry, but you lost me here. What means "works in the Makefile, but not
when it is in the dependency part"? What are "arbitrary" and "implied"
rules" (I know about "implicit" rules, is it that what you mean with
"implied" ones)? And since when make does assume that target and depen-
dency have the same suffix? I simply seem to be the dense to understand
what you're writing... Could you try again with a few examples of what
exactly you want to achieve?
Regards, Jens
--
\   Jens Thoms Toerring  ___  Jens.Toerring@physik.fu-berlin.de
\__________________________  http://www.toerring.de

[ Post a follow-up to this message ]

Jens.Toerring@physik.fu-berlin.de wrote:
> gthorpe@ee.ryerson.ca wrote:
 
[vbcol=seagreen] 
[vbcol=seagreen]
> Sorry, but you lost me here. What means "works in the Makefile, but not
> when it is in the dependency part"? What are "arbitrary" and "implied"
> rules" (I know about "implicit" rules, is it that what you mean with
> "implied" ones)? And since when make does assume that target and depen-
> dency have the same suffix? I simply seem to be the dense to understand
> what you're writing... Could you try again with a few examples of what
> exactly you want to achieve?
>                                    Regards, Jens

Okay, by "works in the Makefile" I mean that if I use $(var:sh) as a command
to update a target, the output of the shell command is properly substituted.
By implied I mean implicit.

I meant to say that make assumes that the PREFIX (not suffix, apologies) is 
the
same for implicit rules. Simply put, I want to say that all UCASE.syn depend
 on
the corresponding ucase.vhd and that there is a common way to build all of
them.

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